The present invention relates to a semiconductor memory device.
FIG. 11 is a block diagram showing a general configuration of a conventional synchronous-type semiconductor memory device (SDRAM). As shown in FIG. 11, the conventional synchronous-type semiconductor memory device includes: a clock buffer 1; a command decoder 2; an address buffer 3; a refresh counter 4; a control signal generator 5; a mode register 6; a memory unit 7; and a DQ buffer 8. The memory unit 7 includes: a memory cell array CA; a column decoder CD; a row decoder RD; and a sense amplifier SA.
The synchronous-type semiconductor memory device having the configuration as described above operates in response to a clock signal, a command, and an address supplied externally. More specifically, the synchronous-type semiconductor memory device reads out and writes data from and to the memory cell array CA via the DQ buffer 8 in synchronism with an internal clock signal int.clk generated on the basis of the clock signal.
FIG. 12 is a block diagram showing a configuration of a data latch unit 15 included in the memory unit 7 of the synchronous-type semiconductor memory device shown in FIG. 11. FIG. 12 also shows: the memory cell array CA formed with a memory cell MC connected to a bit line BL or a complementary bit line/BL; the sense amplifier SA; a reading and writing gate RWG connected in parallel with the sense amplifier SA between the bit line pair; and an input-output port IOP formed by a reading and writing bus connected to the reading and writing gate RWG.
As shown in FIG. 12, the conventional data latch unit 15 is connected in series with the sense amplifier SA via a gate G, and includes a latch circuit LC and a reading gate RG. An output port OP is connected to the reading gate RG.
In the conventional synchronous-type semiconductor memory device having the configuration as described above, read data amplified by the sense amplifier SA are transferred to the latch circuit LC via the gate G and then stored in the latch circuit LC. Thus, even after other data is read out from the memory cell array CA, the data stored in the latch circuit LC can be read independently.
However, when read data is transferred to the latch circuit LC as described above, the read data always need to be amplified by the sense amplifier SA. Therefore, access to the memory cell array CA is interrupted, and data outputted to the sense amplifier SA is destroyed. Thus, when the data outputted to the sense amplifier SA are desired to be used, the data needs to be outputted to the sense amplifier SA again after completion of the operation of transfer to the latch circuit LC. Furthermore, new access to the memory cell array CA during this period is impossible. Therefore, the efficiency of read data output is greatly decreased.
In other words, the operation of reading data from the memory cell array CA and the operation of data transfer to the latch circuit LC are not completely independent of each other; therefore when the transfer operation is given higher priority, efficient reading operation cannot be performed, whereas when the efficient reading operation is given higher priority, the transfer to the latch circuit LC cannot be effected.